modm API documentation
modm::platform::DmaBase Struct Reference
Inheritance diagram for modm::platform::DmaBase:
modm::platform::DmaController modm::platform::Dma

Public Typedefs

using IrqHandler = void (*)(void)
 

Public Types

enum  Channel : uint32_t {
  Channel0, Channel1, Channel2, Channel3,
  Channel4, Channel5, Channel6, Channel7,
  Channel8, Channel9, Channel10, Channel11
}
 
enum  Request : uint32_t {
  Pio0_Tx0 = DREQ_PIO0_TX0, Pio0_Tx1 = DREQ_PIO0_TX1, Pio0_Tx2 = DREQ_PIO0_TX2, Pio0_Tx3 = DREQ_PIO0_TX3,
  Pio0_Rx0 = DREQ_PIO0_RX0, Pio0_Rx1 = DREQ_PIO0_RX1, Pio0_Rx2 = DREQ_PIO0_RX2, Pio0_Rx3 = DREQ_PIO0_RX3,
  Pio1_Tx0 = DREQ_PIO1_TX0, Pio1_Tx1 = DREQ_PIO1_TX1, Pio1_Tx2 = DREQ_PIO1_TX2, Pio1_Tx3 = DREQ_PIO1_TX3,
  Pio1_Rx0 = DREQ_PIO1_RX0, Pio1_Rx1 = DREQ_PIO1_RX1, Pio1_Rx2 = DREQ_PIO1_RX2, Pio1_Rx3 = DREQ_PIO1_RX3,
  Spi0_Tx = DREQ_SPI0_TX, Spi0_Rx = DREQ_SPI0_RX, Spi1_Tx = DREQ_SPI1_TX, Spi1_Rx = DREQ_SPI1_RX,
  Uart0_Tx = DREQ_UART0_TX, Uart0_Rx = DREQ_UART0_RX, Uart1_Tx = DREQ_UART1_TX, Uart1_Rx = DREQ_UART1_RX,
  Pwm_Wrap0 = DREQ_PWM_WRAP0, Pwm_Wrap1 = DREQ_PWM_WRAP1, Pwm_Wrap2 = DREQ_PWM_WRAP2, Pwm_Wrap3 = DREQ_PWM_WRAP3,
  Pwm_Wrap4 = DREQ_PWM_WRAP4, Pwm_Wrap5 = DREQ_PWM_WRAP5, Pwm_Wrap6 = DREQ_PWM_WRAP6, Pwm_Wrap7 = DREQ_PWM_WRAP7,
  I2c0_Tx = DREQ_I2C0_TX, I2c0_Rx = DREQ_I2C0_RX, I2c1_Tx = DREQ_I2C1_TX, I2c1_Rx = DREQ_I2C1_RX,
  Adc = DREQ_ADC, Xip_Stream = DREQ_XIP_STREAM, Xip_SsiTx = DREQ_XIP_SSITX, Xip_SsiRx = DREQ_XIP_SSIRX,
  Dma_Timer0 = DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0, Dma_Timer1 = DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1, Dma_Timer2 = DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2, Dma_Timer3 = DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3,
  Force = DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT
}
 
enum  TransferDataSize : uint32_t {
  Byte = 0, Bit8 = Byte, HalfWord = 1, Bit16 = HalfWord,
  Word = 2, Bit32 = Word
}
 
enum  Priority : uint32_t { Normal = 0, High = 1 }
 

The documentation for this struct was generated from the following file: